
`timescale 1ns / 1ps

`ifndef MYCPU_H
	`define BR_BUS_WD        66
	`define FS_TO_DS_BUS_WD  96
	`define DS_TO_ES_BUS_WD  345
	`define ES_TO_MS_BUS_WD  260
	`define MS_TO_WS_BUS_WD  246
	`define WS_TO_RF_BUS_WD  70
	`define WS_TO_CSR_BUS_WD 129 
	`define WS_EXCEPT_BUS_WD 133 
`endif


`define PC_START    64'h00000000_80000000  
`define OFFSET_TEST 64'h80000000_00000000
`define RISCV_PRIV_MODE_U   0
`define RISCV_PRIV_MODE_S   1
`define RISCV_PRIV_MODE_M   3
`define REG_BUS    63 : 0  

//AXI
`define AXI_ADDR_WIDTH     64
`define AXI_DATA_WIDTH 	   64
`define AXI_ID_WIDTH       4
`define AXI_USER_WIDTH 	   1

`define SIZE_B             2'b00
`define SIZE_H             2'b01
`define SIZE_W             2'b10
`define SIZE_D             2'b11